Method and apparatus for driving the display device, display system, and data processing device

ABSTRACT

It is an object to provide a high-performance display element driving device or the like which can be easily reduced in power consumption and scale. A display element driving device ( 100 ) drives a liquid crystal serving as a capacitive display element. A D/A converter ( 110 ) includes first to Nth charge storage sections ( 112 - 1 ) to ( 112 -N) for receiving first to Nth digital data corresponding an image signal and storing charges corresponding to the values of the first to Nth digital data, and first to Nth connection sections ( 114 - 1 ) to ( 114 -N) for electrically connecting the first to Nth charge storing sections ( 112 - 1 ) to ( 112 -N) and an electrode line ( 130 ) to each other and discharging the stored charges to the electrode line ( 130 ) at a given timing. In this manner, γ-correction of a liquid crystal and D/A conversion can be simultaneously performed, and conversion from RGB to YUV and D/A conversion can be simultaneously performed.

FIELD OF THE INVENTION

The present invention relates to a display driving device for driving adisplay element such as a liquid crystal, a display device including thedisplay element driving device, an information processing apparatusincluding the display device, and a display element driving method.

DESCRIPTION OF THE RELATED ART

FIG. 21 shows a circuit of a conventional data driver disclosed inJapanese Unexamined Patent Publication No. 6-222741. In this datadriver, by using voltages V1 to V9 having nine levels and externallydriven, a 64-level applied voltages are applied to signal lines. Thethree upper bits of digital data of an image signal are converted into8-value data by a decoder 923. Voltage selection circuits 927 and 925select corresponding ones of the voltages V1 to V9 on the basis of the8-value data, and output the selected voltages as VH and VL,respectively. The three lower bits of the digital data of the imagesignal are converted into 8-value data by a decoder 924. A resistordivision scheme D/A converter 926 selects one of voltages obtained byequally dividing the voltages VH and VL by eight and outputs theselected voltage to a signal line as Vout. Even if the conventionalarrangement is used, when the externally input voltages V1 to V9 areoptimized in accordance with the γ characteristics of a liquid-crystalelement, γ-correction can be performed to some extent.

However, since an output voltage is generated by interpolating thevoltages V1 to V9 in the above method, the resultant output voltage isdifferent from a voltage to be displayed in an original state, anddisplay characteristics are degraded disadvantageously.

On the other hand, FIG. 22 shows a case wherein γ-correction isperformed by using a data driver using an analog scheme. In this method,an image signal is converted into analog data by a D/A converter 930. Aγ-correction circuit 934 performs a γ-correction process on the basis ofthe analog data and correction data from a γ-correction table ROM 932.Therefore, analog data subjected to γ-correction is input to ananalog-type data driver 942 in a liquid-crystal display device 940.

However, the analog-type data driver 942 has high power consumptionbecause an analog circuit must be incorporated in the data driver 942,and the data driver 942 is generally improper for a display of aportable computer.

In recent years, it is tried to integrally form the data driver 942 orthe like on a substrate having a TFT (thin-film transistor) 944. Whenthe TFT 944 is integrally formed, a considerable reduction in size ofthe liquid-crystal display device and a reduction in cost can berealized. When such integral formation is to be performed, anincorporated analog circuit must be also constituted by a TFT in theanalog-type data driver. 942. However, when the analog circuit isconstituted by a TFT, the following various problems are posed. That is,the transistor characteristics of the TFT change with time, or it isdifficult to obtain desired performance. In addition, when it is triedto incorporate the γ-correction circuit 934 in the data driver 942, alarge amount of current flows in the γ-correction circuit 934 serving asan analog circuit. For this reason, a problem of a change in transistorcharacteristics of a TFT with time is posed.

As described above, the conventional data driver has various problems.

Some information processing apparatus such as a multi-media terminal ora graphic accelerator do not process an RGB signal used in aliquid-crystal display device, but process an image signal called a YUVor processes both RGB and YUV. When the liquid-crystal display device isused as a display of the information processing apparatus, it is desiredthat both the image signals, i.e., RGB and YUV, can be displayed. Forthis purpose, in a conventional arrangement, a conversion circuit 950 asshown in FIG. 23 is arranged to convert a YUV signal into an RGB signal,D/A conversion is performed by the D/A converter 952, and analog dataobtained by the D/A conversion is applied to a data driver 962.

However, in this arrangement, since an analog-type data driver must beused as the data driver 962, a problem about an increase in powerconsumption is also posed as described above. In addition, there is aproblem of difficulty of the data driver 962 integrally formed on asubstrate on which a TFT 964 is formed.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above problems, and hasas its object to provide a display element driving device, a displaydevice, an information processing apparatus, and a display elementdriving method each of which can obtain a low power consumption, can beincreased in scale, and exhibit high performance.

It is another object of the present invention to provide a displayelement driving device or the like which can compensate for the displaycharacteristics of a display element with an arrangement having lowpower consumption and a small scale.

It is still another object of the present invention to provide a displayelement driving device or the like which can display image signalshaving different formats with an arrangement having a low powerconsumption and a small scale.

It is still another object of the present invention to provide a displayelement driving device or the like which is optimally integrated with asubstrate on which a TFT and the like are formed.

In order to solve the above problems, according to the presentinvention, there is provided a display element driving device comprisinga D/A converter for giving an applied voltage based on a given imagesignal to an electrode line electrically connected to the other side ofa capacitive display element having one side to which a given voltage isapplied.

The D/A converter includes first to Nth charge storage means forrespectively receiving first to Nth digital data corresponding to theimage signal and storing charges corresponding to the values of thefirst to Nth digital data first to Nth connection means for electricallyconnecting the first to Nth charge storage means and the electrode lineto each other and discharging the charges stored in the first to Nthcharge storage means to the electrode line at a given timing.

According to the present invention, for example, in case of N=2, acharge corresponding to the value of the first digital data and a chargecorresponding to the value of the second digital data are stored in thefirst charge storage means and the second charge storage means. When thefirst and second connection means electrically connects the first andsecond charge storage means and the electrode line to each other, thecharges stored in the first and second charge storage means aredischarged to the electrode line. At this time, on the basis of thedischarged charges, capacitances of, e.g., the display element, theelectrode line, and the first and second charge storage means, and thelike, an applied voltage to the electrode line is determined. Accordingto the present invention, the moment D/A conversion is performed,processes such as addition and subtraction processes between the digitaldata are performed or the process multiplying the digital data by givencoefficients can be performed.

The present invention is characterized in that the first to Nth chargestorage means store the charges on the basis of the first to Nth digitaldata can be performed and at least one given voltage. In this manner,when various-given voltages are prepared, or a given voltage is changed,not only a simple addition process of digital data but also variousprocesses such as a subtraction process, a multiplication process of acoefficient can be easily performed.

The present invention is characterized in that the first to Nth chargestorage means include capacitor elements having one sides to which agiven voltage is applied and capacitances which are binarily weighted,and the first to Nth connection means include switches for electricallyconnecting the other sides of the capacitive elements and the electrodeline to each other at once. When the capacitances of the capacitorelements are binarily weighted at, e.g., 1:2:4:8 . . . , an additionprocess, a subtraction process, and the like of digital data can beeasily performed.

The present invention is characterized in that the first to Nth chargestorage means select at least one capacitor element for storing a chargefrom the capacitor elements on the basis of the first to Nth digitaldata, and store a charge in the selected capacitor element at at leastone given voltage. For example, given voltages V1, VC, and −V1(V1−VC=VC−(−V1)), the first charge storage means selects a capacitorelement for storing a charge by V1 and VC on the basis of the firstdigital data, and the second charge storage means selects a capacitorelement for storing a charge by −V1 and VC, thereby making it possibleto perform a subtraction process or the like. When the given voltages tothe first to Nth charge storage means are made different from eachother, a display element driving device which has a small scale and isnot adversely affected by a variation in manufacturing process can berealized.

The present invention is characterized in that digital data having thecomplementary format of 2 is output as the first to Nth digital data,and the capacitance of the capacitor element corresponding to an MSB ofdigital data of capacitor elements included in at least one of the firstto Nth charge storage means is made equal to the capacitance of acapacitor element corresponding to an LSB. For example, when digitaldata to be added is negative, a charge is stored in a capacitorcorresponding to the MSB (Most Significant Bit), so that a subtractionprocess or the like of digital data having the complementary format of 2can be realized.

According to the present invention, there is provided a display elementdriving device comprising a D/A converter for giving an applied voltagebased on a given image signal to an electrode line electricallyconnected to the other side of a capacitive display element having oneside to which a given voltage is applied, characterized in that the D/Aconverter includes first charge storage means for receiving imagedigital data corresponding to the image signal and storing a chargecorresponding to the value of the image digital data, second chargestorage means for receiving correction digital data for compensating forthe display characteristics of the display element and storing a chargecorresponding to the value of the correction digital data, firstcorrection means for electrically connecting the first charge storagemeans and the electrode line to each other and discharging the chargestored in the first charge storage means to the electrode line at agiven timing, and second connection means for electrically connectingthe second charge storage means and the electrode line to each other anddischarging the charge stored in the charge storage means to theelectrode line at the same timing as the given timing.

According to the present invention, D/A conversion of image digitaldata, a γ-correction process of a liquid crystal, and the like, can besimultaneously performed. In addition, the correction process can beaccurately performed, and reductions in power consumption and reductionin scale of the device can also be performed.

The present invention is characterized in that when a change value ofthe applied voltage obtained when the LSB of the image digital datachanges is represented by V1, and a change value of the applied voltageobtained when the LSB of the correction digital data changes isrepresented by V2, a relationship V1>2×V2 is established. In thismanner, a state wherein an applied voltage decreases with respect to anincrease in image digital data is prevented, and normal gradationexpression can be performed.

The present invention is characterized in that when the number of bitsof the image digital data is represented by m, and the number of bits ofthe correction digital data is represented by n, a relationship m≧n isestablished. In this manner, the display element driving device can bereduced in area while making normal gradation expression possible.

According to the present invention, there is provided a display elementdriving device for giving applied voltages VR1, VG1, and VB1 generatedon the basis of digital data DY1, DU1, and DV1 of a YUV signal toelectrode lines for red, green, and blue to which display elements arerespectively electrically connected, characterized by comprising a firstD/A converter for respectively receiving the digital data DY1 and DV1and generating an applied voltage VR1 to the electrode line for red byconversion according to a relational expression VR1=aDY1+bDV1, a secondD/A converter for respectively receiving the digital data DY1, DU1, andDV1 and generating an applied voltage VG1 to the electrode line forgreen by conversion according to a relational expressionVG1=cDY1+dDU1+eDV1, and a third D/A converter for respectively receivingthe digital data DY1 and DU1 and generating an applied voltage VB1 tothe electrode for blue by conversion according to a relationalexpression VB1=fDY1+gDU1.

According to the present invention, D/A conversion, a conversion processfrom YUV to RGB, and the like can be simultaneously performed. In thismanner, a display element driving device which is optimum for aninformation processing apparatus or the like using a YUV signal can beprovided. According to the present invention, various types of YUVsignals such as YUV422 or YUV411 signals can be converted into RGBsignals.

The present invention is characterized by comprising a fourth D/Aconverter for respectively receiving digital data DY2 for generatingVR2, VG2, and VB2 given to second electrode lines for red, green, andblue adjacent to the electrode lines for red, green, and blue and thedigital data DV1 and generating an applied voltage VR2 to the secondelectrode line for red by conversion according to a relationalexpression VR2=aDY2+bDV1, a fifth D/A converter for respectivelyreceiving the digital data DY2, DU1, and DV1 and generating an appliedvoltage VG2 to the second electrode line for green by conversionaccording to the relational expression VG2=cDY2+dDU1+eDV1, and a sixthD/A converter for respectively receiving the digital data DY2 and DU1and generating an applied voltage VB2 to the second electrode line forblue by conversion according to a relational expression VB2=fDY2+gDU1.In this manner, a display element driving device having an arrangementwhich is optimum for conversion of a YUV signal, especially, in a YUV422scheme can be provided.

The present invention is characterized in that the respectivecoefficients a, b, c, d, e, f, and g are determined by at least onegiven voltage and the capacitance of a capacitor element which isincorporated in the D/A converter and in which a charge is stored by thegiven voltage. As described above, when the D/A converters incorporatethe capacitor elements, the coefficients a to g are preferablydetermined by the capacitances (e.g., total capacitance or capacitancecorresponding to the LSB of digital data) of the capacitor elements andthe given voltages.

The present invention is characterized in that the capacitances of thecapacitor elements for determining the respective coefficients a, b, c,d, e f, and g are made equal to each other, and the voltages fordetermining the respective coefficients a, b, c, d, e, f, and g are madedifferent from each other. For example, when capacitances Ca to Cg fordetermining the coefficients a to g are equally set to CEQ, and voltagesVa to Vg for determining the coefficients a to g are made different fromeach other, the coefficients a to g can be set to values which aredifferent from each other. When the coefficient ratio is not an integer,this method is preferable because the method which can make thecapacitances Ca to Cg equal to each other is not easily adverselyaffected by variation in manufacturing process.

The present invention is characterized in that the voltages fordetermining the respective coefficients a, b, c, d, e, f, and g are madeequal to each other, and the capacitances of the capacitor elements fordetermining the respective coefficients a, b, c, d, e, f, and g are madedifferent from each other. For example, when the voltage Va to Vg fordetermining the coefficients a to g are equally set to VEQ, and thecapacitances Ca to Cg for determining the coefficients a to g are madedifferent from each other. The coefficients a to g can be set to valueswhich are made different from each other.

The present invention is characterized in that the display element is acapacitive display element having one side to which a given voltage isapplied; the first D/A converter includes first and second chargestorage means for respectively receiving DY1 and DV1 and storing chargesaccording to the values of the DY1 and DV1 and first and secondconnection means for electrically connecting. The first and secondcharge storage means and the electrode line for red to each other anddischarging the charges stored in the first and second charge storagemeans to the electrode line for red at a given timing; the second D/Aconverter includes third, fourth, and fifth charge storage means forrespectively receiving DY1, DU1, and DV1 and storing charges accordingto the values of the DY1, DU1, and DV1 and third, fourth, and fifthconnection means for electrically connecting the third, fourth, andfifth charge storage means. The electrode line for green to each otherand discharging the charges stored in the third, fourth, and fifthcharge storage means to the electrode line for green at a given timing;and the third D/A converter includes sixth and seventh charge storagemeans for respectively receiving DY1 and DU1 and storing chargesaccording the values of the DY1 and DU1 and sixth and seventh connectionmeans for electrically connecting the sixth and seventh charge storagemeans and the electrode line for blue to each other and discharging thecharges stored in the sixth and seventh charge storage means to theelectrode line for blue at a given timing. When the first to seventhcharge storage means and the first to seventh connection means arearranged as described above, D/A conversion and conversion from YUV toRGB can be realized at a low power consumption with a relatively simplearrangement.

The present invention is characterized in that the display element is acapacitive display element having one side to which a given voltage isapplied; the first D/A converter includes first and second chargestorage means for respectively receiving DY1 and DV1 and storing chargesaccording to the values of the DY1 and DV1 and first and secondconnection means for electrically connecting. The first and secondcharge storage means and the electrode line for red to each other anddischarging the charges stored in the first and second charge storagemeans to the electrode line for red at a given timing; the second D/Aconverter includes third, fourth, and fifth charge storage means forrespectively receiving DY1, DU1, and DV1 and storing charges accordingto the values of the DY1, DU1, and DV1 and third, fourth, and fifthconnection means for electrically connecting. The third, fourth, andfifth charge storage means and the electrode line for green to eachother and discharging the charges stored in the third, fourth, and fifthcharge storage means to the electrode line for green at a given timing;the third D/A converter includes sixth and seventh charge storage meansfor respectively receiving DY1 and DU1 and storing charges according thevalues of the DY1 and DU1 and sixth and seventh connection means forelectrically connecting. The sixth and seventh charge storage means andthe electrode line for blue to each other and discharging the chargesstored in the sixth and seventh charge storage means to the electrodeline for blue at a given timing; the fourth D/A converter includeseighth and ninth charge storage means for respectively receiving DY2 andDV1 and storing charges according to the values of the DY2 and DV1 andeighth and ninth connection means for electrically connecting. Theeighth and ninth charge storage means to the second electrode line forred to each other and discharging the charges stored in the eighth andninth charge storage means to the second electrode line for red at agiven timing; the fifth D/A converter includes tenth, eleventh, andtwelfth charge storage means for respectively receiving DY2, DU1, andDV1 and storing charges according to the values of the DY2, DU1, and DV1and tenth, eleventh, and twelfth connection means for electricallyconnecting the tenth, eleventh, and twelfth charge storage means. Thesecond electrode line for green to each other and discharging thecharges stored in the tenth, eleventh, and twelfth to the secondelectrode line for green at a given timing; and the sixth D/A converterincludes thirteenth and fourteenth charge storage means for respectivelyreceiving DY2 and DU1 and storing charges according to the values of theDY2 and DU1 and thirteenth and fourteenth connection means forelectrically connecting the thirteenth and fourteenth charge storagemeans and the second electrode line for blue to each other anddischarging the charges stored in the thirteenth and fourteenth chargestorage means to the electrode line for blue at a given timing. When thefirst to fourteenth charge storage means and the first to fourteenthconnection means are arranged as described above, D/A conversion andconversion from YUV to RGB can be realized at a low power consumptionwith a relatively simple arrangement.

The present invention is characterized in that digital data DR1, DG1,and DB1 of a RGB signal are further given, and a YUV mode for generatingapplied voltages VR1, VG1, and VB1 on the basis of the digital data DY1,DU1, and DV1 and an RGB mode for generating the applied voltages VR1,VG1, and VB1 on the basis of the digital data DR1, DG1, and DB1 are set.

According to the present invention, not only conversion from YUV to RGBbut also D/A conversion of RGB digital data can also be performed. Inthis manner, a display element driving device which is optimum for aninformation processing apparatus or the like in which both YUV and RGBare set can be provided.

The present invention is characterized by comprising means for, in theRGB mode, inputting DR1 to the first D/A converter in place of DY1 andDV1, inputting DG1 to the second D/A converter in place of DY1, DU1 andDV1, and inputting DB1 to the third D/A converter in place of DY1 andDU1. In this manner, both the conversion processes in the RGB mode andthe YUV mode can be realized by the first to third D/A converters,hardware resources can be effectively used.

The present invention is characterized in that digital data DR1, DG1,DB1, DR2, DG2, and DB2 of an RGB signal are further given, and a YUVmode for generating applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 onthe basis of the digital data DY1, DU1, DV1, and DY2 and an RGB mode forgenerating applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 on thebasis of the digital data DR1, DG1, DB1, DR2, DG2, and DB2 are arranged.In this manner, a display element driving device which is optimum for aninformation processing apparatus or the like in which both YUV422 andRGB are set can be provided.

The present invention is characterized by comprising means for, in theRGB mode, inputting DR1 to the first D/A converter in place of DY1 andDV1, inputting DG1 to the second D/A converter in place of DY1, DU1 andDV1, inputting DB1 to the third D/A converter in place of DY1 and DU1,inputting DR2 to the fourth D/A converter in place of DY2 and DV1,inputting DG2 to the fifth D/A converter in place of DY2, DU1, and DV1,and inputting DB2 to the sixth D/A converter in place of DY2 and DU1. Inthis manner, especially in conversion of a YUV signal in a YUV422scheme, hardware resources can be effectively used.

According to the present invention, there is provided a display elementdriving device for giving first and second applied voltages for red,blue, and green generated on the basis of digital data of a YUV signalto first and second electrode lines for red, green, and blue to whichdisplay elements are respectively electrically connected, characterizedby comprising a first transfer line for sequentially transferringdigital data DY1, DY2, DY3, DY4 . . . DY2K−1 DY2k . . . DYL of the YUVsignal, a second transfer line for sequentially transferring digitaldata DV1, DU1, DV2, DU2 . . . DVK, DUK . . . DVL/2, DUL/2 or DU1, DV1,DU2, DV2 . . . DUK, DVK . . . DUL/2, DVL/2 of the YUV signal, a firstlatch for latching DY2k−1 of the first transfer line, a second latch forlatching DVK or DUK of the second transfer line at a timing which issubstantially the same as that of the first latch, a third latch forlatching DUK or DVK of the second transfer line, a fourth latch forlatching DY2K of the first transfer line at a timing which issubstantially the same as that of the third latch, and first to sixthD/A converters for generating first and second applied voltages for red,green, and blue on the basis of DY2k−1, DVK, DUK, and DY2K latched bythe first to fourth latches.

According to the present invention, data can be caused to flow in thefirst and second transfer lines without any loss, and data transfer tothe first to sixth D/A converters without any loss. For this reason,power consumption and scale of the device can be reduced.

The display device according to the present invention is characterizedby comprising one of the display element driving device described aboveand a display element driven by the display element driving device. Thedisplay device according to the present invention further includes asubstrate on which a switching element consisting of a thin-filmtransistor or a thin-film non-linear element is formed, characterized inthat the display element driving device is integrally formed on thesubstrate. When the display element driving device is integrally formedon the substrate as described above, the display device can be reducedin outside dimension and cost.

According to the present invention, there is provided a display devicecomprising a display element driving device, a display element driven bythe display element driving device, and a substrate on which a switchingelement consisting of a thin-film transistor or a thin-film non-linearelement is formed, characterized in that the display element drivingdevice includes a D/A converter for receiving image digital data andcorrection digital data for compensating for the display characteristicsof the display element and outputting an applied voltage subjected to acorrection process, and the display element driving device is integrallyformed on the substrate.

According to the present invention, since the display element drivingdevice can be integrally formed on the substrate of the TFT, the devicecan be reduced in scale and cost. The circuit in the display elementdriving device can be entirely constituted by a digital-based circuit,and the design for the display element driving device can be simplified.

The invention processing apparatus according to the present invention ischaracterized by comprising any one of the display devices describedabove and at least one image signal output device for outputting animage signal given to the display device. The information processingapparatus according to the present invention comprises a display elementdriving device, a display device including a display element driven bythe display element driving device, a first image signal output devicefor outputting digital data of a YUV signal, and a second image signaloutput device for outputting digital data of an RGB signal, and ischaracterized in that the display element driving device includes meansfor directly converting the digital data of the YUV signal into analogapplied voltages for red, green, and blue to output the analog appliedvoltages when the digital data of the YUV signal is input, andconverting the digital data of the RGB signal into analog appliedvoltages for red, green, and blue to output the analog applied voltageswhen the digital data of the RGB signal is input. In this manner, thedisplay element driving device can be entirely constituted by adigital-based circuit, and an information processing apparatus in whichboth RGB and YUV are set can be reduced in power consumption and size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing the arrangement of Embodiment 1.

FIG. 2 is a view showing a concrete arrangement of a charge storagesection and a connection section.

FIG. 3 is a view showing the arrangement of Embodiment 2.

FIG. 4A is a graph showing the relationship between an applied voltageand the transmittance of a liquid crystal, and FIG. 4B is a graphshowing the relationship between an applied voltage and a γ-correctionvalue.

FIG. 5A is a graph showing the relationship between image digital dataand an applied voltage, FIG. 5b is a graph showing the relationshipbetween image digital data and a correction voltage.

FIG. 6 is a view showing a concrete arrangement of a charge storagesection and a connection section.

FIG. 7 is a view showing a liquid-crystal display device in which a D/Aconverter capable of performing γ-correction is incorporated in a datadriver.

FIG. 8 is a view showing the arrangement of Embodiment 3.

FIG. 9 is a view showing a concrete arrangement of first to third D/Aconverters.

FIG. 10 is a view showing a concrete arrangement of a charge storagesection and a connection section.

FIG. 11 is a view showing a concrete arrangement of a case whereinvoltages used for charge storage are made different from each other.

FIG. 12 is a timing chart for explaining an operation of the arrangementin FIG. 11.

FIGS. 13A to 13C are truth tables for explaining an operation of thearrangement in FIG. 11.

FIG. 14 is a view showing an arrangement of a peripheral circuit of aD/A converter.

FIG. 15 is a timing chart for explaining the arrangement in FIG. 14.

FIG. 16 is a view showing a concrete example of a wiring structure amongfirst to sixth D/A converters, first to fourth latches, and a shiftresistor.

FIG. 17 is a view showing the arrangement of Embodiment 4.

FIG. 18 is a view showing the arrangement of a liquid-crystal displaydevice according to Embodiment 5.

FIGS. 19A to 19E are sectional views showing steps performed when a datadrive is integrally formed on a substrate.

FIG. 20 is a view showing the arrangement of information processingapparatus according to Embodiment 6.

FIG. 21 is a view showing a D/A converter incorporated in a conventionaldata driver.

FIG. 22 is a view sowing a case wherein γ-correction is performed usingan analog-type data driver.

FIG. 23 is a view for explaining conventional YUV/RGB conversion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Embodiment 1

FIG. 1 shows the arrangement of Embodiment 1. A display element drivingdevice according to Embodiment 1 includes a plurality of D/A converters110 and 120 and the like. A D/A converter 110 is to give an appliedvoltage based on a given image signal to an electrode line 130, and acapacitive display element having one side to which a given voltage V0is applied is electrically connected to the electrode line 130. In FIG.1, the capacitor of the display element, the capacitor which isparasitic in the electrode line 130, and the like are represented byCSO. The electrode line 130 may be electrically connected to the displayelement, or a transistor element, a switch element, a resistor element,or the like and may be interposed between the electrode line 130 and thedisplay element.

The D/A converter 110 includes first to Nth charge storage sections112-1 to 112-N and first to Nth connection sections 114-1 to 114-N. Thefirst to Nth charge storage sections 112-1 to 112-N receive first to Nthdigital data corresponding an image signal, and store chargescorresponding to the values of the first to Nth digital data.

In this case, the first to Nth digital data may correspond to at leastan image signal, and the first to Nth digital data are not necessarilydigital data obtained by only converting the image signal. Morespecifically, the first to Nth digital data include various digital datasuch as digital data generated on the basis of, e.g., an image signal ordigital data for correcting the image signal.

Amount of charge stored in the first to Nth charge storage sections112-1 to 112-N may correspond to the values of at least the first to Nthdigital data, and the amounts are not necessarily proportional to thevalues of the first to Nth digital data. For example, the amounts ofstored charge may be determined on the basis of the first to Nth digitaldata and one given voltage or a plurality of given voltages. Morespecifically, the following various methods may be used: any one of theplurality of given voltages is selected on the basis of the first to Nthdigital data, and charges are stored depending on the selected voltage;charges corresponding to multiplication values between the first to Nthdigital data and a given voltage are stored; or the like.

The first to Nth connection sections 114-1 to 114-N electrically connectthe first to Nth charge storage sections 112-1 to 112-N and theelectrode line 130 to each other, and discharge charges stored in thefirst to Nth charge storage sections 112-1 to 112-N to the electrodeline 130 at a given timing. At this time, the first to Nth chargestorage sections 112-1 to 112-N desirably discharge the stored chargesto the electrode line 130 at substantially the same timing. When thecharges are discharged to the electrode line 130, an applied voltage onthe electrode line 130 is determined on the basis of the charge amounts,the capacitance of CSO, the capacitances of the first to Nth chargestorage sections 112-1 to 112-N, and the like. The applied voltage isgiven to the display element to drive the display element. The other D/Aconverters such as a D/A converter 120 have the same arrangements asthat of the D/A converter 110 and generate applied voltages to otherelectrode lines such as an electrode line 132.

FIG. 2 is a view showing a concrete arrangement of a charge storagesection and a connection section. The first and second charge storagesections 112-1 and 112-2 include capacitors (capacitor elements) CA0 toCA3 and CB0 to CB3 each having one side to which a given voltage isapplied. The first and second connection sections 114-1 and 114-2include switches SWA0 to SWA3 and SWB0 to SWB3 for electricallyconnecting the electrode lines 130 and the capacitors CA0 to CA3 and CB0to CB3 to each other at a given timing at once. Here, the capacitancesof the capacitors CA0 to CA3 are binarily weighted. In FIG. 2, the ratioof the capacitances is given by Ca: 2Ca: 4Ca: 8Ca=1:2:4:8. Thecapacitances of the capacitors CB0 to CB3 are binarily weighted, and theratio of the capacitances is given by Cb: 2Cb [4C]b:Cb=1:2:4:1. Thecapacitance of the capacitor CB3 is set to Cb which is equal to that ofthe capacitor CB0 to make it possible to perform subtraction using thecomplementary format of 2 (to be described later). An applied voltageVS0 to the electrode line 130 is initialized to 0 V.

A case wherein (0101)₂=5 is given by the first digital data and(0010)₂=2 is given by the second digital data will be considered.Referring to FIG. 2, one capacitor or a plurality of capacitors forstoring charges is selected on the basis of the values of the first andsecond digital data, and a charge is stored in the selected capacitordepending on one given voltage or a plurality of given voltages. In thisexample, since the first digital data is (0101)₂, CA2 and CA0 areselected, Va serving as a given voltage is applied to CA2 and CA0, avoltage of 0 V is applied to other capacitors. On the other hand, sincethe second digital data is (0010)₂, CB1 is selected, Vb serving as agiven voltage is applied to CB1, and a voltage of 0 V is applied toother capacitors. After charges are stored in the capacitors of thefirst and second charge storage sections 112-1 and 112-2, when theswitches of the first and second connection sections 114-1 and 114-2 areturned on, the applied voltage VS0 to the electrode line 130 changesfrom 0 V serving as an initial value to the value expressed by thefollowing equations:VS0=D1/D2  (1)D1=(4Ca+Ca)×Va+2Cb×Vb=5Ca×Va+2Cb×VbD2=(8Ca+4Ca+2Ca+Ca)+(Cb+4Cb+2Cb+Cb)+CS0  (2)As is apparent from the above equations, since the denominator D2 isconstant without depending on the first and second digital data, themagnitude of the VS0 depends on the numerator D1. More specifically,when the values of the first and second digital data, Ca, Cb, Va, and Vbare set to various values, respectively, VS0 having various values canbe obtained. For example, when Ca=Cb and Va=Vb, D1=7Ca×Va is satisfied,and VS0 corresponding to the sum of values of the first and seconddigital data. According to this embodiment, D/A conversion and anaddition process of the first and second digital data can besimultaneously performed.

A case wherein (0101)₂=5 is given by the first digital data and(1110)₂=−2 is given by the second digital data will be considered. Inthis case, digital data in the complementary format of 2 are input asthe first and second digital data. Since the first digital data is(0101)₂, CA2 and CA0 are selected as in the above description, Va isapplied to the CA2 and CA0. On the other hand, since the second digitaldata (1110)₂ is a negative number because bit 3 serving as the MSB (MostSignificant Bit) is 1. Therefore, the difference between (1110)₂ and(1111)₂ is set, or (1110)₂ is inverted to generate (0001)₂. Bit 0 of theobtained digital data is 1, so that CB0 is selected. In addition, inthis embodiment, CB3 having a capacitance equal to that of CB0corresponding to bit 0 serving as the LSB (Least Significant Bit) isalso selected. A negative voltage −Vb is applied to the CB0 and CB3. Inthis case, the applied voltage VS0 is given by the following equations:VS0=D3/D4  (3)D3=(4Ca+Ca)×Va+(Cb+Cb)×(−Vb)=5Ca×Va+2Cb×VbD4=(8Ca+4Ca+2Ca+Ca)+(Cb+4Cb+2Cb+Cb)+CS0  (4)In this case, the value of the denominator is not different from the D2,and D4=D2 is satisfied. When Ca=Cb and Va=Vb, D3=5Ca×Va−2Ca×Va=3Ca×Va issatisfied. More specifically, according to this embodiment, not only anaddition process but also a subtraction process (addition of a negativenumber) can be performed, D/A converter and the addition/subtractionprocess can be simultaneously performed.

In particular, in this embodiment, when the capacitance of CB3corresponding to the MSB of the CB3 to CB0 is made equal to CB0corresponding to the LSB, subtraction in the complementary format of 2can be performed. More specifically, when subtraction in thecomplementary format of 2 is performed as is well known, data isinverted, and 1 (corresponding to LSB) must be added. In this case, amethod of arranging another capacitor for adding 1 may be used. However,this method increases the circuit scale. In this embodiment, theaddition process of 1 is performed using CB3. When the second digitaldata is a negative number, bit 3 becomes 1; when the second digital datais entirely inverted, bit 3 becomes 0. Therefore, in the subtraction(addition of a negative number) process, in general, charge need not bedischarged from the CB3. In this embodiment, CB3 which is not used inthe addition process of a negative number is effectively used, and theaddition process of 1 is performed by using the CB3 so that the deviceis reduced in scale.

As described above, it is the first characteristic feature of thisembodiment that D/A converter of digital data and various processes suchas addition and subtraction processes between digital data or amultiplication process of a coefficient can be simultaneously performed.Therefore, as will be described later, for example, D/A conversion andγ-correction, or D/A conversion and YUV/RGB conversion can besimultaneously performed. As a result, γ-correction, YUV/RGB conversion,and the like can be performed by a digital processing system, and thedevice can be reduced in scale and power consumption.

It is a second characteristic feature that a display element is drivenby effectively using that the display element to be driven is acapacitive element. More specifically, it is the second characteristicfeature that an applied voltage applied to the electrode line isdetermined on the basis of the display element, the capacitance or thelike of the electrode line, and charge discharged from the chargestorage section. In this manner, a waste current such as a bias currentflowing in an operational amplifier need not be consumed, and the powerconsumption of the device can be reduced. A display element drivingdevice which is optimum for a portable display can be provided.

It is a third characteristic feature of this embodiment that thecapacitance of the electrode line during a disharging operation ofcharge can be made constant without depending on the values of the firstto Nth digital data. More specifically, as described in Equations (2)and (4), the values of denominators D2 and D4 are always kept constantwithout depending on the values of the digital data. Therefore,according to this embodiment, the value of an applied voltage given tothe electrode line can be determined with a simple arrangement andsimple control.

Embodiment 2

Embodiments 2 to 6 (to be described below) mainly exemplify a casewherein the present invention is applied to a data driver (displayelement driving device) for driving a liquid crystal (display element),a liquid-crystal display device (display device) including the datadriver, an information processing apparatus including the liquid-crystaldisplay device, and a liquid-crystal driving method (display elementdriving method).

Embodiment 2 is an embodiment wherein D/A converter and correction ofthe display characteristics of a liquid crystal are simultaneouslyperformed. The arrangement of this embodiment is shown in FIG. 3. Them-bit digital data corresponding to an image signal is latched by animage digital data latch 212. A correction digital data generator 214generates correction digital data on the basis of the image digitaldata. Generation of the correction digital data can be realized by usinga memory such as a γ-correction ROM or a circuit or the like forperforming an arithmetic operation according to a given arithmeticequation (sin wave or the like). When the γ-correction ROM is used, theγ characteristics of a liquid crystal may be actually measured toconstruct a γ-correction table for outputting correction digital datausing image digital data as an address on the ROM. The generatedcorrection digital data is latched by a correction digital data latch216.

A D/A converter 200 includes first and second charge storage sections202 and 204 and first and second connection sections 206 and 208. Thefirst and second charge storage sections 202 and 204 receive imagedigital data and correction digital data and store charges correspondingto these data. The first and second connection sections 206 and 208discharge the stored charges to a signal line (electrode line) 210 at agiven timing. In this manner, according to the principle of Embodiment 1described above, the applied voltage VS0 subjected to γ-correction canbe applied to the signal line 210. Although not shown in FIG. 3, a D/Aconverter having the above arrangement is also connected to a signalline other then the signal line 210.

In FIG. 4A, P indicates an example of V (applied voltage)−T(transmittance) characteristics of a liquid crystal. As described above,in an actual liquid crystal, the transmittance does not linearly changewith respect to a change in applied voltage. For this reason, when aγ-correction process is performed, ideal characteristics indicated by Qcan be obtained. FIG. 4B shows the relationship between the appliedvoltage and a γ-correction amount required to obtain idealcharacteristics.

FIG. 5A shows the relationship between image digital data (4 bits) andthe applied voltage VS0 obtained in this embodiment. In FIG. 5A, Hindicates an applied voltage obtained when the image digital data isdirectly D/A-converted, and I indicates an applied voltage obtained whenγ-correction is performed. The line indicated by I is substantiallysymmetrical with respect to P and Q in FIG. 4A. Therefore, an appliedvoltage represented by I is applied to the liquid crystal, idealcharacteristics Q as shown in FIG. 4A can be obtained. FIG. 5B shows anexample of a correction voltage J (corresponding to 3-bit correctiondigital data) used in this embodiment. When the correction voltage J isadded to H in FIG. 5A, the applied voltage represented by I can beobtained.

As indicated by G in FIG. 5A, in this embodiment, a relationship V1>2×V2is established where V1 corresponds to a change value of the appliedvoltage when the LSB of the image digital data changes; V2 correspondsto a change value of the applied voltage when the LSB of the correctiondigital data changes. When this relationship is established, a statewherein the applied voltage decreases with an increase in image digitaldata or the like can be prevented, and a normal gradation display can beperformed.

In this embodiment, when the number of bits of the image digital data isset to m, and the number of bits of the correction digital data is setto n, the relationship m≧n is established. In this manner, while a statewherein the applied voltage decreases with an increase in image digitaldata is prevented, the area of the capacitors of the first and secondcharge storage sections 202 and 204 and the area of the data driver canbe reduced. More specifically, according to this embodiment, when thecapacitance of the capacitor of the second charge storage section 204 ismade smaller than the capacitance of the capacitor of the first chargestorage section 202, m≧n can be established. In this manner, each timethe number n of bits is made smaller than the number m of bits by 1, thearea of the capacitor can be made ½. According to this embodiment, whena voltage for storing a charge in the capacitor of the second chargestorage section 204 is made smaller than a voltage for storing a chargein the first charge storage section 202, m≧n can be established. In thismanner, the area of the data driver can be reduced to (n+m)/2m. When m=6and n=4 which may be set within a practical range, about 20% of the areacan be saved.

FIG. 6 shows a concrete arrangement of the first and second chargestorage sections 202 and 204 and the first and second connectionsections 206 and 208. Since this arrangement is substantially the sameas the arrangement shown in FIG. 11 (to be described later), adescription thereof will be omitted.

FIG. 7 shows an example of a liquid-crystal display device in which aD/A converter 222 capable of performing a correction process such asγ-correction is incorporated in a data driver 220. The liquid-crystaldisplay device includes the data driver 220 and a substrate 230 on whichat least a TFT 232 (or thin-film non-linear element) driven by the datadriver 220 is formed. The data driver 220 includes the D/A converter 222for receiving image digital data and correction digital data forcompensating for the display characteristics of a liquid crystal andoutputting an applied voltage subjected to a correction process. Aplurality of D/A converters 222 are arranged on the signal lines,respectively. The correction digital data is generated by the correctiondigital data generator 224. In FIG. 7, the data driver 220 is integrallyformed on the substrate 230. When the data driver 220 is integrallyformed on the substrate 230 together with the TFT 232 and the like, thepower consumption of the device can be considerably reduced, and thedevice can be reduced in scale. In particular, according to thearrangement in FIG. 7, the data driver 220 can be entirely constitutedby a digital signal system. Therefore, an analog circuit need not beincorporated in the data driver 220, and the power consumption can befurther reduced. A large current need not be caused to flow in the TFTconstituting the circuit of the data driver 220, and a problem caused bya change in transistor characteristics of the TFT with time can beprevented. If the circuit is a digital circuit, the circuit can beoperated by a TFT having relatively low performance without any problem.For this reason, a design for the circuit or the like becomes simple.When the correction digital data generator 224 is also incorporated inthe data driver 220 and integrally formed on the substrate 230, thepower consumption of the device can be further reduced, and the devicecan be reduced in scale. Note that a D/A converter having thearrangement as shown in FIG. 3 or 6 is especially preferable as the D/Aconverter 222 with respect to low power consumption or the like.However, a D/A converter having another arrangement may be employed.

Embodiment 3

Embodiment 3 is an embodiment for simultaneously performing D/Aconversion and YUV/RGB conversion. The arrangement of Embodiment 3 isshown in FIG. 8. A data driver of Embodiment 3 applies voltages VR1,VG1, and VB1, generated on the basis of digital data DY1, DU1, and DV1of a YUV signal, to signal lines 312, 314, and 316 for red, green, andblue that are electrically connected to liquid-crystal elements,respectively. The data driver includes first, second, and third D/Aconverters 300, 302, and 304. In this case, the first D/A converter 300receives DY1 and DV1 to generate VR1 by conversion according to arelational expression VR1=aDY1+bDV1. The second D/A converter 302receives DY1, DU1, and DV1 to generate VG1 by conversion according to arelational expression VG1=cDY1+dDU1+eDV1. The third D/A converter 304receives DY1 and DU1 to generate VB1 by conversion according to arelational expression VB1=fDY1+gDU1. In this case, as the arrangementsof the first to third D/A converters 300 to 304, the arrangements shownin FIGS. 1, 2, or the like of Embodiment 1 are especially preferable.However, other arrangements may be used.

Here, the YUV signal is a color signal which is generally used in atelevision set or a video cassette recorder. Reference symbol Yindicates a total luminance (brightness) of red, green, and blue,reference symbol U indicates the color difference of red, and referencesymbol V indicates the color difference of blue. In the YUV signal, itis considered that human eyes are more insensible of a change in colorthan of a change in luminance. That is, with respect to four pixels, Yinformation is given to all the four pixels, U information and Vinformation are given to two pixels each. This scheme is called YUV422(4:2:2). Furthermore, a scheme called YUV411 (4:1:1) in which rates of Uinformation and V information are more reduced may be used.

In recent years, in many multi-media terminals or the like usingpersonal computers, both the YUV and RGB signals are set. On the otherhand, a RGB signal is generally used for a display of a liquid-crystaldisplay device. Therefore, when a liquid-crystal display device is usedas the display of a multi-media terminal or the like, a YUV signal mustbe converted into an RGB signal. As conversion equations, the followingequations may be used:R=Y+1.367VG=Y−0.703125V−0.34375UB=Y+1.7345U  (5)

where Y=0 to 255, U=−128 to 127, V=−128 to 127.

The first to third D/A converters 300 to 304 simultaneously perform theconversion expressed by the above equations and D/A conversion. Morespecifically, the first to third D/A converters 300 to 304 directlygenerate analog circuit applied voltages VR1 to VB1 for red, green, andblue from digital data DY1 to DU1 of an input YUV signal. In thismanner, a circuit in the data driver can be entirely constituted by adigital system. Therefore, an analog which consumes a lot of power andis not easily designed need not be arranged, and the device can bereduced in power consumption and scale.

When the YUV422 is employed, fourth to sixth D/A converters 306 to 310having the arrangement shown in FIG. 8 are preferably arranged. Here,the fourth to sixth D/A converter 306 receives digital data DY2 anddigital data DV1 for generating applied voltages VR2, VG2, and VB2 tosignal lines 318 to 322 adjacent to the signal lines 312 to 316 andgenerates VR2 by conversion according to a relational expressionVR2=aDY2+bDV1. The fifth D/A converter 308 receives DY2, DU1, and DV1and generates VG2 by conversion according to a relational expressionVG2=cDY2+dDU1+eDV1. The sixth D/A converter 310 receives DY2 and DU1 andgenerates an applied voltage VB2 by conversion according to a relationalexpression VB2=fDY2+gDU1. As described above, when YUV422 is used, inorder to obtain VR1 to VB1 and VR2 to VB2, i.e., 2 pixels×RGB appliedvoltages, four digital data DY1, DY2, DU1, and DV1 are given. On theother hand, when YUV411 is used, in order to obtain 4 pixels×RGB appliedvoltages, six digital data DY1, DY2, DY3, DY4, DU1, and DV1 may begiven.

FIG. 9 shows a concrete arrangement of the first to third D/A converters300 to 304. Referring to FIG. 9, the first D/A converter 300 includesfirst and second charge storage sections 330 and 332 and first andsecond connection sections 334 and 336, the second D/A converter 302includes third to fifth charge storage sections 340 to 343 and third tofifth connection sections 344 to 347, and the third D/A converter 304includes sixth and seventh charge storage sections 350 and 352 and sixthand seventh connection sections 354 and 356. Since the operationalprinciple of these charge storage sections and connection sections hasbeen described in Embodiment 1, a description thereof will be omitted.The fourth to sixth D/A converters 306 to 310 have the same arrangementas that of the first to third D/A converters 300 to 304 except for inputdigital data.

FIG. 10 shows another concrete arrangement of the second D/A converter302. The third, fourth, and fifth charge storage section 340, 342, and342 include capacitors CY7 to CY0, CU7 to CU0, and CV7 to CV0 havingbinarily weighted capacitances, respectively. The third, fourth, andfifth connection sections 344, 346, and 347 include switches SW7 to SW0,SWU7 to SWU0, and SWV7 to SWV0. The second D/A converter 302 performsD/A conversion and YUV/RGB conversion according to the followingarithmetic equation:VG1=cDY1+dDU1+eDV1  (6)=DY1−0.703125DU1−0.34375DV1

In this embodiment, DY1, DU1, and DV1 are input in the complementaryformat of 2, and DU1 and DV1 have both positive and negative values. Forthis reason, a subtraction (addition of a negative number) process mustbe performed. In this embodiment, the capacitances of the capacitors CU7and CV7 corresponding to the MBSs of DU1 and DV1 are made equal tocapacitances Cu and Cv of the capacitors CU0 and CV0, respectively.

As described in Equation (6) described above, since coefficients c, d,and e of DY1, DU1, and DV1 are different from each other, thecapacitances of capacitors (capacitors corresponding LSBs), voltagesused in storing charges, and the like must be different from each otheramong the first to third charge storage sections 340 to 343. When thecapacitances of the capacitors are made different from each other, forexample, Cy:Cu:Cv=c:d:e must be established. However, this condition isnot preferable in consideration of a variation in manufacturing process.For example, a case wherein a capacitor using a first polysilicon layeras a lower electrode, a second polysilicon layer as an upper electrode,and an insulation film between the first and second polysilicon layersas a dielectric material is formed will be considered. At this time, inorder to cause the ratio of Cy to Cv to satisfy c:e=1:0.34375, the arearatio of the pattern shape on the upper electrode must satisfyc:e=1:0.34375. However, although a pattern shape having an area ratiowhich can be represented by integers can be easily formed, a patternshape having an area ratio which is not represented by integers cannotbe easily formed. In addition, even if the pattern is formed, the arearatio is considerably influenced by a variation in manufacturing processor the like, and a correct applied voltage cannot be easily generated.

Therefore, in this embodiment, the capacitances of capacitorscorresponding to LSBs are made equal to each other (Cy=Cu=Cv), andvoltages used in storing charges are made different from each otheramong the first to third charge storage sections 340 to 343. Forexample, when voltages VY, VU, and VV are used to store charges of CY7to CY0, CU7 to CU0, and CV7 to CV0, VY:VU:VV=c:d:e is established. Inthis manner, the pattern shapes of the upper electrodes of, e.g., CY0,CU0, and CV0 can be made equal to each other, so that simple design canbe obtained, and an influence of the variation in manufacturing processon an obtained applied voltage can be optimized. In this case, althoughthe capacitances of, e.g., CY0 and CY1 are different from each other,this difference has no problem because the ratio of these capacitancesis an integer ratio.

In order to obtain an integer capacitance ratio regardless of avariation in manufacturing process, a plurality of capacitors havingupper electrodes having the same pattern shapes may be connected inparallel to each other.

FIG. 11 shows a concrete arrangement in which voltages used to storecharges are made different from each other. FIG. 11 corresponds to aconcrete example of the third D/A converter 304. FIG. 12 is a timingchart showing an operation of the circuit in FIG. 11, and FIGS. 13A to13C are truth tables.

As shown in FIG. 13A, when Y7 is 0, the switch SB7 is turned on, and avoltage VC is selected; when VC=0 V, no charge is stored in CY7. In thiscase, VC is not necessarily set to 0 V. Note that VB-Y>VC isestablished, VC corresponds to an intermediate voltage between VB−U1 andVB−U2, and VB−Y−VC>VB−U1−VC=VC−VB−U2 is established (see FIG. 12).

On the other hand, when Y7 is 1, the switch SA7 is turned on, and avoltage VB−Y is selected. A charge is stored in CY7 by the voltage VB−Y.

As shown in FIG. 13B, when U7 is 0, the switch SC7 is turned on, VC isselected; when U7 is 1, the switch SD7 is turned on, and VB−U2 isselected. The voltage VB−U2 is a voltage on the negative side withreference to VC. A case wherein U7 is 1 means that the digital data DU1in the complementary format of 2 is a negative number. When a negativenumber is added in the complementary format of 2, data must be inverted,and 1 (corresponding to LSB) must be added. In this embodiment, theaddition of 1 is performed by the charge stored in CU7. Morespecifically, in this embodiment, the capacitance of CU7 correspondingto an MSB is made equal to the capacitance of CU0. When data to be addedis negative, a charge is stored in CU7 by the voltage VB−U2 which is onthe negative side.

As shown in FIG. 13C, both U7 and U6 are 0, the switch SC6 is turned on,and VC is selected. When U7 and U6 are 1 and 0, respectively, the switchSD6 is turned on, a charge is stored in CU6 by the voltage VB−U1 whichis on the positive side, and a positive number is added. On the otherhand, when U7 and U6 are 1 and 0, respectively, the switch SE6 is turnedon, a charge is stored in CU6 by the voltage VB−U2 which is on thenegative side, and a negative number is added. When both U7 and U6 are1, VC is selected.

In the timing chart shown in FIG. 12, DY1 and DU1 are changed from 0 to7 in the first half. In the second half, although DY1 is changed from 0to 7, DU1 is changed from 0 to −7. At this time, an example of an outputresult is shown as VB1. A SET signal for turning on/off switches SSY7 toSSY0 and SSU7 to SSU0 and an ENBL signal for turning on/off the switchesSSY7 to SSY0 and SSU7 to SSU0 alternately go to H and L as shown in FIG.12. At this time, the SET signal and the ENBL signal are desirably setin a non-overlap state.

FIG. 14 is an arrangement of first to sixth latches 420 to 430 and ashift resistor 466 which are peripheral circuits of first to ninth D/Aconverters 400 to 416, and FIG. 15 is a timing chart for explainingoperations of these circuits. As shown in FIG. 15, in a first transferline 460, digital data DY1, DY2, DY3, DY4 . . . DY2K−1, DY2K . . . DY640of a YUV signal are sequentially transferred. On the other hand, in asecond transfer line 462, digital data DV1, DU1, DV2, DU2 . . . DVK, DUK. . . DV320, DU320 of a YUV signal are sequentially transferred.

The first latch 420 latches DY2K−1 of the first transfer line 460, andthe second latch 422 latches DVK of the second transfer line 462 at atiming which is substantially the same as that of the first latch 420.More specifically, switches 432 and 434 are simultaneously turned on bya signal B1 from the shift resistor 466, and, i.e., digital data DY1 andDV1 are latched by the first and second latches 420 and 422,respectively. The third latch 424 latches DUK of the second transferline 462, and the fourth latch 426 latches DY2K of the first transferline 460 at a timing which is substantially equal to that of the thirdlatch 424. More specifically, switches 436 and 438 are simultaneouslyturned on by a signal B2 from the shift resistor 466, and, e.g., digitaldata DU1 and DY2 are latched by the third and fourth latches 424 and426, respectively. The first to sixth D/A converters 400 to 410 generatefirst and second applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 forred, green, and blue on the basis of DY2−1, DVK, DUK, and DY2K, e.g.,DY1, DV1, DU1, and DY2 which are latched by the first to fourth latches420 to 426. In this case, although the first to sixth D/A converters 400to 410 preferably have the arrangement shown in FIGS. 8 and 9 or thelike, an arrangement other than the arrangement shown in FIGS. 8 and 9or the like may also be used.

When data is transferred and latched at a timing as shown in FIG. 15,the number of transfer lines and the number of latches can be optimized,and the device can be reduced in scale. That is, as shown in FIG. 15,the first and second transfer lines 460 and 462 can be caused to flowwithout any loss, and data can also be transferred to the first to sixthD/A converters 400 to 410 without any loss.

In FIG. 15, although data DV1, DU1, DV2, DU2 . . . DVK, DUK . . . DV320,and DU320 are transferred in this order, the order of DV and DU may bereversed, i.e., the DU1, DV1, DU2, DV2 . . . DUK, DVK . . . DU320, andDV320 may be transferred in this order. When YUV411 is used, latches forDu and DV are preferably arranged for each of first to fourth appliedvoltages for red, blue, and green, e.g., each of 4 pixels×RGB.

FIG. 16 shows another concrete example of a wiring structure among firstto sixth D/A converters 470 to 480, first to fourth latches 482 to 488,and a shift resistor 490. The specific characteristic feature in FIG. 16is that, e.g., VR−Y, VR−V1, and VR−V2 are used in the first and fourthD/A converters 470 and 476 in common. In addition, VG−Y to VG−V2, VB−Yto VB−U2, and VC are used in the D/A converters in common. As describedin FIG. 11, in the arrangement in FIG. 11, the values of voltages VB−Y,VC, VB−U1, and VB−U2 are adjusted to adjust coefficients by which DY1and DU1 are multiplied. In this manner, the capacitors CY6 to CY0 andCU6 to CU0 can have the same capacitances and upper electrodes havingthe same patterns. CU7 is equal to CY0 and CU0. In FIG. 16, e.g., VR−Yto VR−V2 are used in the first and fourth D/A converters 470 and 476 incommon, and the capacitors included in the first and fourth D/Aconverters 470 and 476 can be made equal to each other. Similarly, thecapacitors of the second and fifth D/A converters 472 and 478 can bemade equal to each other, and the capacitors of the third and sixth D/Aconverters 474 to 480 can be made equal to each other. In this manner, alayout pattern of the D/A converters can be regulated. As a result, thedevice can be reduced in scale, and a data driver which is difficult tobe adversely affected by a variation in manufacturing process or thelike can be provided.

Embodiment 4

FIG. 17 shows an arrangement of Embodiment 4. Embodiment 4 is anembodiment related to a data driver comprising a mode (to be referred toas a YUV mode hereinafter) for converting digital YUV into analog RGBand a mode (to be referred to as an RGB mode hereinafter) for convertingdigital RGB into analog RGB. More specifically, as shown in FIG. 17, inEmbodiment 4, digital data of an RGB signal is further given. Embodiment4 comprises a YUV mode for generating applied voltages VR1, VG1, VB1,VR2, VG2, and VB2 on the basis of the digital data DY1, DU1, DV1, andDY2 and an RGB mode for generating applied voltages VR1, VG1, VB1, VR2,VG2, and VB2 on the basis of the digital data DR1, DG1, DB1, DR2, DG2,and DB2.

In the RGB mode, data input to first to sixth D/A converters 500 to 510are switched as described below. More specifically, DR1 is input to thefirst D/A converter 500 in place of DY1 and DV1. DG1 is input to thesecond D/A converter 502 in place of DY1, DU1, and DV1. DB1 is input tothe third D/A converter 504 in place of DY1 and DU1. Similarly, DR2,DG2, and DB2 are input to the fourth, fifth, and sixth D/A converters506, 508, and 510 in place of DY2 and DV1, DY2, DY1, and DV1, and DY2and DU1, respectively.

The above switching process will be further described below. In a firsttransfer line 532, data (to be referred to as RGB/YUV data hereinafter)for determining whether a target image signal is an RGB signal or a YUVsignal is transferred. DR, DU, and DV are transferred in a secondtransfer line 534, DG and DY are transferred in a third transfer line536, and DB is transferred in a fourth transfer line 538. The switches540 to 546 are turned on by a B1 signal from a shift resistor 530, sothat data flowing in the first to fourth transfer lines 532 to 538 arelatched by an RGB/YUV switching circuit 524 and first to third latches512 to 516. Switches 548 to 554 are turned on by a B2 signal from theshift resistor 530, and data flowing in the first to fourth transferlines 532 to 538 are latched by the RGB/YUV switching circuit 524 andfourth to sixth latches 518 to 522.

In the YUV mode, DU1, DY1, DV1, and DY2 are latched by the first,second, fourth, and fifth latches 512, 514, 518, and 520, respectively.When the RGB/YUV switching circuit 524 is controlled, switches 560, 562,564, 566, 568, and 570 are turned off, and switches 580, 582, 584, 586,588, and 590 are turned on. In this manner, the same signal connectionrelationship as in FIG. 14 is obtained, and, as in the case shown inFIG. 14, desired digital data are input to the first to sixth D/Aconverters 500 to 510. A conversion process for converting digital YUVinto analog applied voltages VR1 to VB1 and VR2 to VB2 is performed.

On the other hand, in the RGB mode, DR1, DG1, DB1, DR2, DG2, and DB2 arelatched by fourth to sixth latches 512 to 522. When the RGB/YUVswitching circuit 524 is controlled, the switches 580 to 590 are turnedoff, and switches 560 to 570 are turned off. In this manner, RGB digitaldata are input to the first to sixth D/A converters 500 to 510. Aconversion process of converting digital RGB into the analog appliedvoltages VR1 to VB1 and VR2 to VB2 is performed.

According to this embodiment, both digital YUV and digital RGB can behandled. Therefore, digital YUV and RGB can be directly received from amulti-media terminal in which both YUV and RGB are set, a graphicaccelerator, or the like without using a D/A converter or the like, andan analog applied voltage can be generated. In this manner, the datadriver can be entirely constituted by a digital system, and the devicecan be reduced in power consumption and scale.

Embodiment 5

Embodiment 5 is an embodiment related to a liquid-crystal display deviceintegrally formed on a substrate on which a TFT is formed. Referring toFIG. 18, a data driver 600 is a data driver being capable of performingthe γ-correction described above, YUV/RGB conversion, and simultaneoususe of YUV and RGB, and the like. In FIG. 18, the data driver 600, agate driver 602, an active matrix section 608 (TFTs 604 and 606 arearranged in a matrix) are integrally formed on a substrate 610. Whenthese circuits are integrally formed on the substrate 610, theliquid-crystal display device can be reduced in outside dimension andcost.

FIGS. 19A to 19E are sectional views showing the steps when the datadriver 600 or the like is constituted by a CMOS self-align-typepolysilicon TFT, and the active matrix section 608 is constituted by anLDD-type polysilicon TFT. As shown in FIG. 19A, an insulating film forpreventing an insulating material from being diffused from the substrateis deposited on a glass substrate 71, and a polysilicon thin film 72 isdeposited on the insulating film. The crystallinity of the polysiliconthin film 72 must be improved to increase field-effect mobility.Therefore, a polysilicon thin film is recrystallized by using laserannealing, solid-phase growing method, or the like, or a film obtainedby crystallizing an amorphous silicon thin film into a polysilicon filmis used. After the polysilicon thin film 72 is patterned to have anisland shape, a gate insulating film 73 is deposited.

As shown in FIG. 19B, after a gate electrode 74 is formed, a portionserving as an N-channel TFT is covered with a mask material 75, boronions are doped at a high concentration to form a sourcexdrain portion ofa P-channel TFT.

As shown in FIG. 19C, the mask material is removed, and phosphorous ionsare doped in the front surface at a low concentration. In addition, asshown in FIG. 19D, a portion serving as a P-channel TFT and the LDDportion of pixel TFTs are covered with a mask material, and phosphorousions are doped at a high concentration. The TFTs of the active matrixsection (pixel section) has an arrangement in which an LDD portionconstituted by an n-type high-resistance polysilicon thin film(n⁻poly-si) is formed between a sourcexdrain portion constituted by ann-type low-resistance polysilicon thin film (n⁻poly-si). In this manner,the OFF current of the TFTs of the active matrix section are suppressedto be sufficiently low, and generation of crosstalk or the like can beprevented.

Finally, as shown in FIG. 19E, an insulating interlayer 76 is formed,and a wiring structure is constituted by a metal thin film 77, pixelelectrodes are constituted by a transparent conductive film 79 or thelike, and a passivation film 78 is formed. As a result, an active matrixsubstrate in which a data driver is integrally formed is completed. Thesubstrate is subjected to an aligning process, and a counter substratesubjected to the same aligning process is caused to oppose thesubstrate. A liquid crystal is sealed between these substrates, so thata liquid crystal display device is completed.

Embodiment 6

Embodiment 6 is an embodiment related to an information processingapparatus (multi-media terminal or the like) including a liquid-crystaldisplay device and an image signal output device for outputting an imagesignal given to the liquid-crystal display device. FIG. 20 shows anarrangement of Embodiment 6.

A liquid-crystal display device 700 includes an active matrix section710 in which data drivers 702 and 704, a gate driver 706, a TFT 708, andthe like are formed. As an image information reproducing device 720, forexample, a DVD, a CD-ROM, a digital video cassette recorder, or the likemay be used. Static image information of, e.g., the JPEG standardsoutput from the image information reproducing device 720 is input to astatic image information decoder 722. The static image informationdecoder 722 decodes the static image information which is subjected tocompression or the like of the JPEG standards to output a digital YUVsignal. Similarly, moving image information of, e.g., the MPEG standardsoutput from the image information reproducing device 720 is input to amoving image information decoder 724. The moving image informationdecoder. 724 decodes the moving image information which is subjected tocompression or the like of the MPEG standards to output a digital YUVsignal. On the other hand, as a computer processing image storage device726, a VRAM or the like may be used. A digital RGB signal is output fromthe computer processing image storage device 726.

A digital YUV signal output from a first image signal output device (theimage information reproducing device 720, the static image informationdecoder 722, and the moving image information decoder 724) and a digitalRGB signal output from a second image signal output device (the computerprocessing image storage device 726) are input to an image signalselector 728. One of the YUV signal and the RGB signal is selected to beinput to the data drivers 702 and 704. Input/output timings of thesignals are controlled by an RGB/YUV timing controller 730 and acomputer 732.

The data drivers 702 and 704 include means which, when digital data ofthe YUV signal is input, directly convert the digital data into analogapplied voltages for red, green, and blue to output the analog appliedvoltages and, when digital data of the RGB signal is input, convert thedigital data into analog applied voltages for red, green, and blue tooutput the applied voltage. As such means, means having the arrangementdescribed in FIG. 17 is especially preferable. However, means having anarrangement other than the arrangement can be employed. When the meansis arranged in the data driver, the data driver can be entirelyconstituted by a digital-base circuit, and the device can be reduced inpower consumption, scale, and the like.

It is preferable to integrally form the data drivers 702 and 704 and thegate driver 706 on a substrate on which the active matrix 710 is formed.In addition, the static image information decoder 722, the moving imageinformation decoder 724, the image signal selector 728, and the RGB/YUVtiming controller 730 may be incorporated in a data driver, so that thedata driver may be integrally formed on a substrate on which the activematrix 710 is formed.

The present invention is not limited to Embodiments 1 to 6 describedabove, and various modified embodiments can be effected within the rangeof the spirit and scope of the invention.

For example, the above embodiments describe a case wherein the presentinvention is applied to γ-correction of a liquid crystal and YUV/RGBconversion. However, the present invention can be applied to othervarious conversion processes.

The present invention can also be applied to a display element drivingdevice other than a data driver, a display device other than aliquid-crystal display device, and an information processing apparatusother than a multi-media terminal. In addition, the present inventioncan be applied to not only active-matrix-type liquid-crystal displaydevices using thin-film transistors, thin-film non-linear elements(e.g., MIMs), and the like and data drivers for the active-matrix-typeliquid-crystal display devices, but also all liquid-crystal displaydevices including simple-matrix-type liquid-crystal display devices anddata drivers for the liquid-crystal display devices.

1. A display element driving device comprising: a D/A converter forapplying a voltage based on a given image signal to an electrode linethat is electrically connected to a capacitive display element havingone side to which a given voltage is applied, wherein said D/A converterincludes: first charge storage means for receiving image digital datacorresponding to the image signal and for storing a charge correspondingto a value of the image digital data; second charge storage means forreceiving correction digital data for compensating for displaycharacteristics of said display element and for storing a chargecorresponding to a value of the correction digital data; firstconnection means for electrically connecting said first charge storagemeans to said electrode line and for discharging the charge stored insaid first charge storage means to said electrode line at a giventiming; and second connection means for electrically connecting saidsecond charge storage means to said electrode line and for dischargingthe charge stored in said charge storage means to said electrode line ata substantially same timing as the given timing.
 2. The display elementdriving device according to claim 1, wherein when a change value of theapplied voltage obtained when a least significant bit of the imagedigital data changes is represented by V1, and a change value of theapplied voltage obtained when a least significant bit of the correctiondigital data changes is represented by V2, a relationship of V1>2×V2 isestablished.
 3. The display element driving device according to claim 1,wherein when the number of bits of the image digital data is representedby m, and the number of bits of the correction digital data isrepresented by n, then a relationship of m≧n is established.
 4. Adisplay device comprising: a display element driving device, the displayelement driving device including a D/A converter, the D/A converterhaving a first section for receiving image digital data and a secondsection for receiving correction digital data for compensating the imagedigital data for a display characteristic of the display element; adisplay element driven by said display element driving device; and asubstrate on which a switching element selecting a display element andincluding a thin-film transistor or a thin-film non-linear element isformed, an output voltage from the D/A converter based on the imagedigital data and correction digital data being applied to an electrodeline, and said display element driving device being integrally formed onsaid substrate.
 5. An information processing apparatus comprising saiddisplay device according to claim 4 and at least one image signal outputdevice for outputting an image signal to said display device.
 6. Adisplay device comprising: a display element driving device, the displayelement driving device including a D/A converter, the D/A converterhaving a first section for receiving image digital data and a secondsection for receiving correction digital data for compensating the imagedigital data for a display characteristic of the display element; and adisplay element driven by the display element driving device, an outputsignal from the D/A converter based on the image digital data and thecorrection digital data being supplied to the display element through anelectrode line.
 7. A display element driving method for applying avoltage based on a given image signal to an electrode line electricallyconnected to a capacitive display element having one side to which agiven voltage is applied, the method comprising the steps of: inputtingimage digital data corresponding to the image signal to first chargestorage means, and storing a charge corresponding to a value of theimage digital data in said first charge storage means; inputtingcorrection digital data for compensating for display characteristics ofsaid display element to second charge storage means, and storing acharge corresponding to a value of the correction digital data in saidsecond charge storage means, wherein said first charge storage means iselectrically connected to said electrode line and the charge stored insaid first charge storage means is discharged to said electrode line ata given timing, said second charge storage means and said electrode lineare electrically connected to each other, and the charge stored in saidcharge storage means is discharged to said electrode line at a sametiming as the given timing.
 8. A display element driving devicecomprising: a D/A converter for applying a voltage based on a givenimage signal to an electrode line that is electrically connected to acapacitive display element having one side to which a given voltage isapplied, wherein said D/A converter includes: first charge storagecapacitor that receives image digital data corresponding to the imagesignal and that stores a charge corresponding to a value of the imagedigital data; second charge storage capacitor that receives correctiondigital data for compensating for display characteristics of saiddisplay element and that stores a charge corresponding to a value of thecorrection digital data; first switch that electrically connects saidfirst charge storage capacitor to said electrode line and thatdischarges the charge stored in said first charge storage capacitor tosaid electrode line at a given timing; and second switch thatelectrically connects said second charge storage capacitor to saidelectrode line and that discharges the charge stored in said chargestorage capacitor to said electrode line at a substantially same timingas the given timing.
 9. The display device according to claim 6, thecorrection digital data being γ correction type digital data.
 10. Thedisplay device according to claim 6, the first section of the D/Aconverter receiving m bits of image digital data for every n bits ofimage digital data received by the second section of the D/A converter,wherein m≧n.